3D Lattice of Gates

I maintain that there exist multiple computers, and each computer was initialized with up to 2 ^ 65,536 = 2 ^ (2 ^ 16) bits of information. The no. of computers that exist = the total possible no. of initial configurations = 2 ^ (2 ^ 65,536). Our universe is a simulation running on one of those computers, and that simulation was written by sentient, digital-based life forms that evolved from simpler digital life forms. Each computer is composed of a 3D lattice of wires and logic gates. Each intersection in the lattice has 57 possible configurations (more on that later). The size of this lattice is, in terms of width and depth, up to 2 ^ 17 cells in extent, and each grid cell has 57 possible configurations, or 6 bits of information. So each horizontal plane of the lattice has (2 ^ 17) x (2 ^ 17) x (2 ^ 6) = 2 ^ 40 bits of information. The height of the lattice = (2 ^ 65,536) divided by (2 ^ 40) = 2 ^ 65,496 horizontally-oriented planes.

Each grid intersection of the lattice can be one of 4 types of logic gates (NOT, AND, OR, and switch, or memory bit), or simply an intersection of between 0 and 6 wires, or a crossover intersection of 4 wires in a vertically-oriented plane (width/height). In a simple (non-crossover) intersection, there are 8 possible wiring configurations: 2 ^ 3, or 2 (wire present or absent) raised to the power of the number of directions (up, right, and above). We don't count the down, left, and below directions, as those wires were already counted in (belong to) adjacent grid intersections. The up/down wires do not physically make contact with the left/right wires in a crossover intersection.

All of the up to 3 wires making contact with a logic gate (2 going in and 1 coming out) are in the same vertically-oriented plane (width/height). The NOT gate is a special case: it has 1 wire coming in and 1 wire going out. There are 12 possible wiring configurations for each logic gate: (4 choose 2) x 2 = (the total no. of ways of choosing 2 input directions out of a total of 4 directions) x (2 possible output directions) = 6 x 2 = 12. There are also 12 possible wiring configurations for a NOT gate: (4 possible input directions) x (3 possible output directions for each input direction).

So there are 57 possible configurations for each grid intersection: 8 + 1 + (4 x 12) = 8 simple intersections + 1 crossover intersection + (4 logic gates x 12). Note that the switch or memory-bit logic gate is actually composed of 4 simpler logic gates: 2 OR gates and 2 NOT gates, wired together such that the output of each OR gate goes into a NOT gate, and the output of each NOT gate is redirected into the opposite OR gate.

It is possible to use solely NAND gates instead of using AND, OR, and NOT gates, but the logic is simpler to design and understand if you don't use NAND gates.

In the near future I intend to design the wiring diagram of the computer that hosts the simulation of our universe. When I visit my sister in Victoria, in the last 2 weeks in August, I intend to take my laptop and work on designing that computer.