Equivalency of Lattices

I maintain that it doesn't really matter if the lattices I'm using to build my giant computers have 16 or 57 possible configurations per grid intersection, whether they're 2D, 3D, or a higher no. of dimensions, whether they're based on: NAND gates; or AND, OR, NOT, and bit gates; or all 8 possible 2-input/1-output symmetric logic gates (AND, NAND, OR, NOR, XOR, EQ, always 0, and always 1). The important features are that each grid intersection can contain a single logic gate (or a set of 2 or 4 logic gates in the case of the "bit" gate) or a simple intersection of wires (and adding support for crossover intersections makes it easier to lay out the wiring diagram of these computers, but it's not absolutely necessary).

I would argue that all possible lattices of the sort described above are equivalent (so it doesn't really matter which design I choose). Alan Turing proved that all digital computers are equivalent to each other and to the single-tape Turing machine. I can't prove that all lattices are equivalent, as I'm a mediocre mathematician (well, a programmer at any rate) who graduated from a second-rate university (Drexel University, of which I graduated exactly one quarter prior to that university being one of the first universities in North America to require all freshmen to buy microcomputers, in their case, Macs). I spent my first year at a top school, the University of Waterloo, and my last 3 years at Drexel. I don't think I ever had to prove a single theorem in all those 3 years, unlike at Waterloo. I took a semester of Advanced Calculus at the University of Toronto; they didn't have that course at Drexel. I never owned a Mac, my first computer was an Atari 1040 ST (more primitive and cheaper than the Macs of its day; my former boss owned an Atari computer dealership).

My next task is to design the 3D wiring diagram of my 16-state lattice (7 configurations with NAND gates, 1 crossover, and 8 simple intersections). The word size of all these computers is 65,536 bits long, so it's certainly a challenging task to lay it all out. Armed with the experience of designing a decoder with a 3-bit address out of logic gates (based on a simpler design I pulled off the Net) and knowing the simple wiring diagram of a bistable latch (memory bit), I think I can pull it off. I'll be working on that during my 12-day vacation in Victoria, BC, visiting my sister. The next task will be to document the whole Computaverse theory, including that wiring diagram, on my web site (after writing it up in Word). And finally, publicizing my theory in various computer forums. That's the Computaverse game plan.